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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
| commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
| tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/max10/cells_map.v | |
| parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
| download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip | |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/max10/cells_map.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/max10/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v index b74007ff8..9229fae51 100755..100644 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -62,7 +62,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function |