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authorBenjamin Barzen <bbarzen@barzen.io>2023-04-23 01:24:36 +0200
committerGitHub <noreply@github.com>2023-04-22 16:24:36 -0700
commit861142923719aa84afc3bdf3c24a9a36e5d5fbaf (patch)
tree6962a1e6128f3df3c099924942cb43ec2780b443 /passes
parent7efc50367ed8f582001a5a293a9cd51f788f6a13 (diff)
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ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/abc9_ops.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9766e81cb..ed4d4bdfb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
auto offset = i.first.offset;
- auto O = module->addWire(NEW_ID);
+ if (!cell->hasPort(i.first.name))
+ continue;
auto rhs = cell->getPort(i.first.name);
+ if (offset >= rhs.size())
+ continue;
+ auto O = module->addWire(NEW_ID);
#ifndef NDEBUG
if (ys_debug(1)) {