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| author | Benjamin Barzen <bbarzen@barzen.io> | 2023-04-23 01:24:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-22 16:24:36 -0700 |
| commit | 861142923719aa84afc3bdf3c24a9a36e5d5fbaf (patch) | |
| tree | 6962a1e6128f3df3c099924942cb43ec2780b443 | |
| parent | 7efc50367ed8f582001a5a293a9cd51f788f6a13 (diff) | |
| download | yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.tar.gz yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.tar.bz2 yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.zip | |
ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch
* Add simplified testcase
* Also fix xaiger writer for under-width output ports
* Remove old testcase
* Missing top-level input port
* Fix tabs
---------
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 | ||||
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 | ||||
| -rw-r--r-- | tests/arch/xilinx/bug3670.v | 13 | ||||
| -rw-r--r-- | tests/arch/xilinx/bug3670.ys | 3 |
4 files changed, 26 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e223f185e..68c2ff52f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -274,6 +274,10 @@ struct XAigerWriter continue; auto offset = i.first.offset; + auto rhs = cell->getPort(i.first.name); + if (offset >= rhs.size()) + continue; + #ifndef NDEBUG if (ys_debug(1)) { static pool<std::pair<IdString,TimingInfo::NameBit>> seen; @@ -281,7 +285,7 @@ struct XAigerWriter log_id(cell->type), log_id(i.first.name), offset, d); } #endif - arrival_times[cell->getPort(i.first.name)[offset]] = d; + arrival_times[rhs[offset]] = d; } if (abc9_flop) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 9766e81cb..ed4d4bdfb 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) continue; auto offset = i.first.offset; - auto O = module->addWire(NEW_ID); + if (!cell->hasPort(i.first.name)) + continue; auto rhs = cell->getPort(i.first.name); + if (offset >= rhs.size()) + continue; + auto O = module->addWire(NEW_ID); #ifndef NDEBUG if (ys_debug(1)) { diff --git a/tests/arch/xilinx/bug3670.v b/tests/arch/xilinx/bug3670.v new file mode 100644 index 000000000..c7dd18079 --- /dev/null +++ b/tests/arch/xilinx/bug3670.v @@ -0,0 +1,13 @@ +module bug3670(input we, output [31:0] o1, o2, output o3); + // Completely missing port connections, where first affected port + // (ADDRARDADDR) has a $setup delay + RAMB36E1 ram1(.DOADO(o1)); + + // Under-specified input port connections (WEA is 4 bits) which + // has a $setup delay + RAMB36E1 ram2(.WEA(we), .DOADO(o2)); + + // Under-specified output port connections (DOADO is 32 bits) + // with clk-to-q delay + RAMB36E1 ram3(.DOADO(o3)); +endmodule diff --git a/tests/arch/xilinx/bug3670.ys b/tests/arch/xilinx/bug3670.ys new file mode 100644 index 000000000..772072c1e --- /dev/null +++ b/tests/arch/xilinx/bug3670.ys @@ -0,0 +1,3 @@ +read_verilog bug3670.v +read_verilog -lib -specify +/xilinx/cells_sim.v +abc9 |