From 861142923719aa84afc3bdf3c24a9a36e5d5fbaf Mon Sep 17 00:00:00 2001 From: Benjamin Barzen Date: Sun, 23 Apr 2023 01:24:36 +0200 Subject: ABC9: Cell Port Bug Patch (#3670) * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung --- passes/techmap/abc9_ops.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 9766e81cb..ed4d4bdfb 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -674,8 +674,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) continue; auto offset = i.first.offset; - auto O = module->addWire(NEW_ID); + if (!cell->hasPort(i.first.name)) + continue; auto rhs = cell->getPort(i.first.name); + if (offset >= rhs.size()) + continue; + auto O = module->addWire(NEW_ID); #ifndef NDEBUG if (ys_debug(1)) { -- cgit v1.2.3