From fca168797e86b6e501bf3b571380a9daf09d728b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 25 Feb 2022 16:15:32 +0100 Subject: Fix for last clock edge data --- passes/sat/sim.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index a5494a088..f28fd21e5 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1125,7 +1125,7 @@ struct SimWorker : SimShared try { fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) { log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString()); - bool did_something = time < stopCount; // FIXME + bool did_something = false; for(auto &item : inputs) { std::string v = fst->valueOf(item.second); did_something |= top->set_state(item.first, Const::from_string(v)); @@ -1138,8 +1138,6 @@ struct SimWorker : SimShared } if (did_something) update(); - else - log("nothing to update.\n"); write_output_step(time); bool status = top->checkSignals(); -- cgit v1.2.3