diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/sat | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/sat')
-rw-r--r-- | passes/sat/expose.cc | 68 | ||||
-rw-r--r-- | passes/sat/freduce.cc | 12 | ||||
-rw-r--r-- | passes/sat/miter.cc | 58 | ||||
-rw-r--r-- | passes/sat/sat.cc | 4 | ||||
-rw-r--r-- | passes/sat/share.cc | 93 |
5 files changed, 122 insertions, 113 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 22b724d53..a84faf792 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,8 +83,8 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections_.count("\\Q")) - dffsignals.add(sigmap(it.second->connections_.at("\\Q"))); + if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q")) + dffsignals.add(sigmap(it.second->get("\\Q"))); } for (auto &it : module->wires) { @@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL: info.cell = it.second; if (info.cell->type == "$dff") { - info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL: } if (info.cell->type == "$adff") { - info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections_.at("\\ARST")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool(); - std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits; for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); @@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL: } if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") { - info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); info.clk_polarity = info.cell->type == "$_DFF_P_"; - info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") { - info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections_.at("\\R")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; continue; } } @@ -514,11 +514,11 @@ struct ExposePass : public Pass { for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cells.at(cell_name); - std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->connections_.at("\\Q") = cell_q_bits; + cell->set("\\Q", cell_q_bits); } RTLIL::Wire *wire_q = new RTLIL::Wire; @@ -536,7 +536,7 @@ struct ExposePass : public Pass { connect_q.second.append(RTLIL::SigBit(wire_q, i)); set_q_bits.insert(wire_bits_vec[i]); } - module->connections_.push_back(connect_q); + module->connect(connect_q); RTLIL::Wire *wire_d = new RTLIL::Wire; wire_d->name = wire->name + sep + "d"; @@ -544,7 +544,7 @@ struct ExposePass : public Pass { wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); add_new_wire(module, wire_d); - module->connections_.push_back(RTLIL::SigSig(wire_d, info.sig_d)); + module->connect(RTLIL::SigSig(wire_d, info.sig_d)); RTLIL::Wire *wire_c = new RTLIL::Wire; wire_c->name = wire->name + sep + "c"; @@ -552,14 +552,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); add_new_wire(module, wire_c); if (info.clk_polarity) { - module->connections_.push_back(RTLIL::SigSig(wire_c, info.sig_clk)); + module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections_["\\A"] = info.sig_clk; - c->connections_["\\Y"] = wire_c; + c->set("\\A", info.sig_clk); + c->set("\\Y", wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -570,14 +570,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); add_new_wire(module, wire_r); if (info.arst_polarity) { - module->connections_.push_back(RTLIL::SigSig(wire_r, info.sig_arst)); + module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections_["\\A"] = info.sig_arst; - c->connections_["\\Y"] = wire_r; + c->set("\\A", info.sig_arst); + c->set("\\Y", wire_r); } RTLIL::Wire *wire_v = new RTLIL::Wire; @@ -586,7 +586,7 @@ struct ExposePass : public Pass { wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); add_new_wire(module, wire_v); - module->connections_.push_back(RTLIL::SigSig(wire_v, info.arst_value)); + module->connect(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -628,18 +628,18 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections_.count(p->name) != 0) - sig = cell->connections_.at(p->name); + if (cell->connections().count(p->name) != 0) + sig = cell->connections().at(p->name); sig.extend(w->width); if (w->port_input) - module->connections_.push_back(RTLIL::SigSig(sig, w)); + module->connect(RTLIL::SigSig(sig, w)); else - module->connections_.push_back(RTLIL::SigSig(w, sig)); + module->connect(RTLIL::SigSig(w, sig)); } } else { - for (auto &it : cell->connections_) + for (auto &it : cell->connections()) { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); @@ -653,9 +653,9 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) - module->connections_.push_back(RTLIL::SigSig(it.second, w)); + module->connect(RTLIL::SigSig(it.second, w)); else - module->connections_.push_back(RTLIL::SigSig(w, it.second)); + module->connect(RTLIL::SigSig(w, it.second)); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 517e6713c..d5336ca01 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -610,7 +610,7 @@ struct FreduceWorker for (auto &it : module->cells) { if (ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> inputs, outputs; - for (auto &port : it.second->connections_) { + for (auto &port : it.second->connections()) { std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector(); if (ct.cell_output(it.second->type, port.first)) outputs.insert(bits.begin(), bits.end()); @@ -624,7 +624,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && it.second->type == "$_INV_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y")))); + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y")))); } int bits_count = 0; @@ -719,14 +719,14 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); - inv_cell->connections_["\\A"] = grp[0].bit; - inv_cell->connections_["\\Y"] = inv_sig; + inv_cell->set("\\A", grp[0].bit); + inv_cell->set("\\Y", inv_sig); } - module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); + module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); } else - module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); + module->connect(RTLIL::SigSig(grp[i].bit, grp[0].bit)); rewired_sigbits++; } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9e151cdfc..96aa10ba3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, w2->width = w1->width; miter_module->add(w2); - gold_cell->connections_[w1->name] = w2; - gate_cell->connections_[w1->name] = w2; + gold_cell->set(w1->name, w2); + gate_cell->set(w1->name, w2); } if (w1->port_output) @@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, w2_gate->width = w1->width; miter_module->add(w2_gate); - gold_cell->connections_[w1->name] = w2_gold; - gate_cell->connections_[w1->name] = w2_gate; + gold_cell->set(w1->name, w2_gold); + gate_cell->set(w1->name, w2_gate); RTLIL::SigSpec this_condition; @@ -165,9 +165,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections_["\\A"] = RTLIL::SigSpec(w2_gold, i); - eqx_cell->connections_["\\B"] = RTLIL::State::Sx; - eqx_cell->connections_["\\Y"] = gold_x.extract(i, 1); + eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i)); + eqx_cell->set("\\B", RTLIL::State::Sx); + eqx_cell->set("\\Y", gold_x.extract(i, 1)); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); @@ -179,9 +179,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->connections_["\\A"] = w2_gold; - or_gold_cell->connections_["\\B"] = gold_x; - or_gold_cell->connections_["\\Y"] = gold_masked; + or_gold_cell->set("\\A", w2_gold); + or_gold_cell->set("\\B", gold_x); + or_gold_cell->set("\\Y", gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; @@ -189,9 +189,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->connections_["\\A"] = w2_gate; - or_gate_cell->connections_["\\B"] = gold_x; - or_gate_cell->connections_["\\Y"] = gate_masked; + or_gate_cell->set("\\A", w2_gate); + or_gate_cell->set("\\B", gold_x); + or_gate_cell->set("\\Y", gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; @@ -199,10 +199,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections_["\\A"] = gold_masked; - eq_cell->connections_["\\B"] = gate_masked; - eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections_["\\Y"]; + eq_cell->set("\\A", gold_masked); + eq_cell->set("\\B", gate_masked); + eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->get("\\Y"); } else { @@ -212,10 +212,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections_["\\A"] = w2_gold; - eq_cell->connections_["\\B"] = w2_gate; - eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections_["\\Y"]; + eq_cell->set("\\A", w2_gold); + eq_cell->set("\\B", w2_gate); + eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->get("\\Y"); } if (flag_make_outcmp) @@ -224,7 +224,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name); w_cmp->port_output = true; miter_module->add(w_cmp); - miter_module->connections_.push_back(RTLIL::SigSig(w_cmp, this_condition)); + miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } all_conditions.append(this_condition); @@ -236,15 +236,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->connections_["\\A"] = all_conditions; - reduce_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - all_conditions = reduce_cell->connections_["\\Y"]; + reduce_cell->set("\\A", all_conditions); + reduce_cell->set("\\Y", miter_module->addWire(NEW_ID)); + all_conditions = reduce_cell->get("\\Y"); } if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->connections_["\\A"] = all_conditions; - assert_cell->connections_["\\EN"] = RTLIL::SigSpec(1, 1); + assert_cell->set("\\A", all_conditions); + assert_cell->set("\\EN", RTLIL::SigSpec(1, 1)); } RTLIL::Wire *w_trigger = new RTLIL::Wire; @@ -257,8 +257,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->connections_["\\A"] = all_conditions; - not_cell->connections_["\\Y"] = w_trigger; + not_cell->set("\\A", all_conditions); + not_cell->set("\\Y", w_trigger); miter_module->fixup_ports(); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index cc041391b..71eba2f7f 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -321,7 +321,7 @@ struct SatHelper if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { - for (auto &p : c.second->connections_) + for (auto &p : c.second->connections()) if (ct.cell_output(c.second->type, p.first)) show_drivers.insert(sigmap(p.second), c.second); import_cell_counter++; @@ -505,7 +505,7 @@ struct SatHelper final_signals.add(sig); } else { for (auto &d : drivers) - for (auto &p : d->connections_) { + for (auto &p : d->connections()) { if (d->type == "$dff" && p.first == "\\CLK") continue; if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C") diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 01acf50df..0ee5af186 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -77,7 +77,7 @@ struct ShareWorker for (auto &pbit : portbits) { if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { - std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->connections_.at("\\S")).to_sigbit_set(); + std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -256,9 +256,11 @@ struct ShareWorker if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; unsigned_cell->check(); @@ -267,17 +269,17 @@ struct ShareWorker bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec a1 = c1->connections_.at("\\A"); - RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); + RTLIL::SigSpec a1 = c1->get("\\A"); + RTLIL::SigSpec y1 = c1->get("\\Y"); - RTLIL::SigSpec a2 = c2->connections_.at("\\A"); - RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); + RTLIL::SigSpec a2 = c2->get("\\A"); + RTLIL::SigSpec y2 = c2->get("\\Y"); int a_width = std::max(a1.size(), a2.size()); int y_width = std::max(y1.size(), y2.size()); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -286,14 +288,14 @@ struct ShareWorker supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections_["\\A"] = a; - supercell->connections_["\\Y"] = y; + supercell->set("\\A", a); + supercell->set("\\Y", y); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -312,7 +314,10 @@ struct ShareWorker if (score_flipped < score_unflipped) { - std::swap(c2->connections_.at("\\A"), c2->connections_.at("\\B")); + RTLIL::SigSpec tmp = c2->get("\\A"); + c2->set("\\A", c2->get("\\B")); + c2->set("\\B", tmp); + std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); modified_src_cells = true; @@ -323,9 +328,11 @@ struct ShareWorker { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; modified_src_cells = true; @@ -334,9 +341,11 @@ struct ShareWorker if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\B").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_b = unsigned_cell->get("\\B"); + new_b.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\B", new_b); } unsigned_cell->parameters.at("\\B_SIGNED") = true; modified_src_cells = true; @@ -356,13 +365,13 @@ struct ShareWorker if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") b_signed = false; - RTLIL::SigSpec a1 = c1->connections_.at("\\A"); - RTLIL::SigSpec b1 = c1->connections_.at("\\B"); - RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); + RTLIL::SigSpec a1 = c1->get("\\A"); + RTLIL::SigSpec b1 = c1->get("\\B"); + RTLIL::SigSpec y1 = c1->get("\\Y"); - RTLIL::SigSpec a2 = c2->connections_.at("\\A"); - RTLIL::SigSpec b2 = c2->connections_.at("\\B"); - RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); + RTLIL::SigSpec a2 = c2->get("\\A"); + RTLIL::SigSpec b2 = c2->get("\\B"); + RTLIL::SigSpec y2 = c2->get("\\Y"); int a_width = std::max(a1.size(), a2.size()); int b_width = std::max(b1.size(), b2.size()); @@ -372,20 +381,20 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections_.at("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections_.at("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y"); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y"); } else { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); } - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -397,16 +406,16 @@ struct ShareWorker supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\B_WIDTH"] = b_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections_["\\A"] = a; - supercell->connections_["\\B"] = b; - supercell->connections_["\\Y"] = y; + supercell->set("\\A", a); + supercell->set("\\B", b); + supercell->set("\\Y", y); supercell->check(); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -438,7 +447,7 @@ struct ShareWorker for (auto &bit : pbits) { if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") - forbidden_controls_cache[cell].insert(bit.cell->connections_.at("\\S").extract(bit.offset, 1)); + forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -532,9 +541,9 @@ struct ShareWorker std::set<int> used_in_b_parts; int width = c->parameters.at("\\WIDTH").as_int(); - std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->connections_.at("\\A")); - std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->connections_.at("\\B")); - std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->connections_.at("\\S")); + std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->get("\\A")); + std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->get("\\B")); + std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->get("\\S")); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) @@ -572,7 +581,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections_.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); + module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); cells_to_remove.insert(cell); } |