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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 09:35:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 09:35:45 -0700 |
| commit | 914074a07c14709523cc72084e1673bd3c2eaf30 (patch) | |
| tree | 2e2d19b812f870f8d10cf94f52f97a4f2887ddfb /passes/sat | |
| parent | 6931a3a47da5119ac44449ef117f3985e2fda417 (diff) | |
| download | yosys-914074a07c14709523cc72084e1673bd3c2eaf30.tar.gz yosys-914074a07c14709523cc72084e1673bd3c2eaf30.tar.bz2 yosys-914074a07c14709523cc72084e1673bd3c2eaf30.zip | |
Update from master
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 50ab38063..71ce1683d 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -42,7 +42,7 @@ struct dff_map_bit_info_t { bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map) { - if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name)) + if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) return false; if (wire->port_input) return false; |