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authorEddie Hung <eddie@fpgeh.com>2019-05-28 09:35:45 -0700
committerEddie Hung <eddie@fpgeh.com>2019-05-28 09:35:45 -0700
commit914074a07c14709523cc72084e1673bd3c2eaf30 (patch)
tree2e2d19b812f870f8d10cf94f52f97a4f2887ddfb /passes
parent6931a3a47da5119ac44449ef117f3985e2fda417 (diff)
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Update from master
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/wreduce.cc2
-rw-r--r--passes/sat/expose.cc2
2 files changed, 1 insertions, 3 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index cfe4b4067..1fbc41082 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -465,12 +465,10 @@ struct WreduceWorker
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++) {
- log_dump(initsig[i], remove_init_bits.count(initsig[i]));
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
w->attributes.at("\\init") = new_initval;
- log_dump(w->name, initval, new_initval);
}
}
}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 50ab38063..71ce1683d 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -42,7 +42,7 @@ struct dff_map_bit_info_t {
bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
{
- if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name))
+ if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
return false;
if (wire->port_input)
return false;