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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
| commit | 432a09af80f7dcba9fd517a001e3a1954c99537e (patch) | |
| tree | 1adf4d0a7cdf929de445b000255dfa8ca23663a5 /passes/sat | |
| parent | b567f03c266b0c44d81a24dde2ed538f1db05d4e (diff) | |
| download | yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.gz yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.bz2 yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.zip | |
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f9e7783a9..24aba22f3 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); @@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); |