diff options
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f9e7783a9..24aba22f3 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); @@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); |