diff options
-rw-r--r-- | kernel/rtlil.cc | 19 | ||||
-rw-r--r-- | kernel/rtlil.h | 1 | ||||
-rw-r--r-- | passes/hierarchy/submod.cc | 5 | ||||
-rw-r--r-- | passes/techmap/techmap.cc | 12 |
4 files changed, 17 insertions, 20 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 17e4a2733..1a6e386ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -782,14 +782,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); - for (auto &it : cells) { - new_mod->cells[it.first] = new RTLIL::Cell; - new_mod->cells[it.first]->name = it.second->name; - new_mod->cells[it.first]->type = it.second->type; - new_mod->cells[it.first]->connections = it.second->connections; - new_mod->cells[it.first]->parameters = it.second->parameters; - new_mod->cells[it.first]->attributes = it.second->attributes; - } + for (auto &it : cells) + new_mod->addCell(it.first, it.second); for (auto &it : processes) new_mod->processes[it.first] = it.second->clone(); @@ -912,6 +906,15 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) return cell; } +RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) +{ + RTLIL::Cell *cell = addCell(name, other->type); + cell->connections = other->connections; + cell->parameters = other->parameters; + cell->attributes = other->attributes; + return cell; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ RTLIL::Cell *cell = new RTLIL::Cell; \ diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e1e4a54bc..fbd6e719d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -302,6 +302,7 @@ struct RTLIL::Module RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); // The add* methods create a cell and return the created cell. All signals must exist in advance. diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 204f899a0..be580ca04 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -162,10 +162,7 @@ struct SubmodWorker } for (RTLIL::Cell *cell : submod.cells) { - RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type); - new_cell->connections = cell->connections; - new_cell->parameters = cell->parameters; - new_cell->attributes = cell->attributes; + RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); for (auto &conn : new_cell->connections) for (auto &bit : conn.second) if (bit.wire != NULL) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e8385844d..94cb1e8dd 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -183,22 +183,18 @@ struct TechmapWorker for (auto &it : tpl->cells) { RTLIL::IdString c_name = it.second->name; - RTLIL::IdString c_type = it.second->type; - - if (!flatten_mode && c_type.substr(0, 2) == "\\$") - c_type = c_type.substr(1); if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_") c_name = orig_cell_name; else apply_prefix(cell->name, c_name); - RTLIL::Cell *c = module->addCell(c_name, c_type); - c->connections = it.second->connections; - c->parameters = it.second->parameters; - c->attributes = it.second->attributes; + RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); + if (!flatten_mode && c->type.substr(0, 2) == "\\$") + c->type = c->type.substr(1); + for (auto &it2 : c->connections) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); |