use the new isPublic() in a few places

2 files changed, 6 insertions, 6 deletions

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 51b4ad0f1..6923ae3d0 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -114,25 +114,25 @@ struct EquivMakeWorker
 		Module *gate_clone = gate_mod->clone();
 
 		for (auto it : gold_clone->wires().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				wire_names.insert(it->name);
 			gold_clone->rename(it, it->name.str() + "_gold");
 		}
 
 		for (auto it : gold_clone->cells().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gold_clone->rename(it, it->name.str() + "_gold");
 		}
 
 		for (auto it : gate_clone->wires().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				wire_names.insert(it->name);
 			gate_clone->rename(it, it->name.str() + "_gate");
 		}
 
 		for (auto it : gate_clone->cells().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gate_clone->rename(it, it->name.str() + "_gate");
 		}
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index d15c8d183..a43ecec5a 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -35,7 +35,7 @@ struct EquivPurgeWorker
 	{
 		if (sig.is_wire()) {
 			Wire *wire = sig.as_wire();
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				if (!wire->port_output) {
 					log("  Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
 					wire->port_output = true;
@@ -62,7 +62,7 @@ struct EquivPurgeWorker
 	{
 		if (sig.is_wire()) {
 			Wire *wire = sig.as_wire();
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				if (!wire->port_output) {
 					log("  Module input: %s\n", log_signal(wire));
 					wire->port_input = true;