use the new isPublic() in a few places

9 files changed, 17 insertions, 17 deletions

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 6326b4b15..f8fe715c8 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -290,11 +290,11 @@ struct RenamePass : public Pass {
 				dict<RTLIL::Cell *, IdString> new_cell_names;
 
 				for (auto wire : module->selected_wires())
-					if (wire->name[0] == '\\' && wire->port_id == 0)
+					if (wire->name.isPublic() && wire->port_id == 0)
 						new_wire_names[wire] = NEW_ID;
 
 				for (auto cell : module->selected_cells())
-					if (cell->name[0] == '\\')
+					if (cell->name.isPublic())
 						new_cell_names[cell] = NEW_ID;
 
 				for (auto &it : new_wire_names)
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index a4ad861f6..0c96f8c5d 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -368,7 +368,7 @@ struct ShowWorker
 			const char *shape = "diamond";
 			if (wire->port_input || wire->port_output)
 				shape = "octagon";
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
 						id2num(wire->name), shape, findLabel(wire->name.str()),
 						nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 20627d601..0f63b91c5 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -211,7 +211,7 @@ struct SpliceWorker
 		std::vector<Wire*> mod_wires = module->wires();
 
 		for (auto wire : mod_wires)
-			if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) {
+			if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) {
 				if (!design->selected(module, wire))
 					continue;
 				RTLIL::SigSpec sig = sigmap(wire);
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index ed51fdc24..0d84c73db 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -81,7 +81,7 @@ struct statdata_t
 
 		for (auto wire : mod->selected_wires())
 		{
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				num_pub_wires++;
 				num_pub_wire_bits += wire->width;
 			}
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 51b4ad0f1..6923ae3d0 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -114,25 +114,25 @@ struct EquivMakeWorker
 		Module *gate_clone = gate_mod->clone();
 
 		for (auto it : gold_clone->wires().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				wire_names.insert(it->name);
 			gold_clone->rename(it, it->name.str() + "_gold");
 		}
 
 		for (auto it : gold_clone->cells().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gold_clone->rename(it, it->name.str() + "_gold");
 		}
 
 		for (auto it : gate_clone->wires().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				wire_names.insert(it->name);
 			gate_clone->rename(it, it->name.str() + "_gate");
 		}
 
 		for (auto it : gate_clone->cells().to_vector()) {
-			if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+			if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
 				cell_names.insert(it->name);
 			gate_clone->rename(it, it->name.str() + "_gate");
 		}
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index d15c8d183..a43ecec5a 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -35,7 +35,7 @@ struct EquivPurgeWorker
 	{
 		if (sig.is_wire()) {
 			Wire *wire = sig.as_wire();
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				if (!wire->port_output) {
 					log("  Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
 					wire->port_output = true;
@@ -62,7 +62,7 @@ struct EquivPurgeWorker
 	{
 		if (sig.is_wire()) {
 			Wire *wire = sig.as_wire();
-			if (wire->name[0] == '\\') {
+			if (wire->name.isPublic()) {
 				if (!wire->port_output) {
 					log("  Module input: %s\n", log_signal(wire));
 					wire->port_input = true;
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 5370881d3..bd9856e81 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -207,7 +207,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 	if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
 		return !(w2->port_input && w2->port_output);
 
-	if (w1->name[0] == '\\' && w2->name[0] == '\\') {
+	if (w1->name.isPublic() && w2->name.isPublic()) {
 		if (regs.check(s1) != regs.check(s2))
 			return regs.check(s2);
 		if (direct_wires.count(w1) != direct_wires.count(w2))
@@ -220,7 +220,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 		return w2->port_output;
 
 	if (w1->name[0] != w2->name[0])
-		return w2->name[0] == '\\';
+		return w2->name.isPublic();
 
 	int attrs1 = count_nontrivial_wire_attrs(w1);
 	int attrs2 = count_nontrivial_wire_attrs(w2);
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 15abee73e..95e0e0944 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 		dict<SigBit, int> bit_user_cnt;
 
 		for (auto wire : module->wires()) {
-			if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
+			if (wire->name.isPublic() && wire->attributes.count(ID::src))
 				sigmap.add(wire);
 		}
 
@@ -468,7 +468,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 				}
 
 				if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
-					if (bit.wire->name[0] == '\\')
+					if (bit.wire->name.isPublic())
 						sigmap.add(bit);
 					continue;
 				}
@@ -493,7 +493,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 						entry.src.insert(s);
 
 					SigBit bit = sigmap(conn.second[i]);
-					if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
+					if (bit.wire && bit.wire->name.isPublic() && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
 						for (auto &s : bit.wire->get_strpool_attribute(ID::src))
 							entry.src.insert(s);
 						entry.wire = bit.wire->name;
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index d7bf125d1..9fdac6147 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -1365,7 +1365,7 @@ struct SatPass : public Pass {
 
 		if (show_public) {
 			for (auto wire : module->wires())
-				if (wire->name[0] == '\\')
+				if (wire->name.isPublic())
 					shows.push_back(wire->name.str());
 		}