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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-09-14 12:43:18 +0200 |
|---|---|---|
| committer | N. Engelhardt <nak@symbioticeda.com> | 2020-09-14 12:43:18 +0200 |
| commit | 32381907972e16d5f72705eaf5350b731a9d71c8 (patch) | |
| tree | 73c08e35387cb9df6d69cf0d9129b03e115fd69c /passes/cmds/splice.cc | |
| parent | 4af04be0b7bb493a86a35a60f3b18d88df6b8ea9 (diff) | |
| download | yosys-32381907972e16d5f72705eaf5350b731a9d71c8.tar.gz yosys-32381907972e16d5f72705eaf5350b731a9d71c8.tar.bz2 yosys-32381907972e16d5f72705eaf5350b731a9d71c8.zip | |
use the new isPublic() in a few places
Diffstat (limited to 'passes/cmds/splice.cc')
| -rw-r--r-- | passes/cmds/splice.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 20627d601..0f63b91c5 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -211,7 +211,7 @@ struct SpliceWorker std::vector<Wire*> mod_wires = module->wires(); for (auto wire : mod_wires) - if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) { + if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) { if (!design->selected(module, wire)) continue; RTLIL::SigSpec sig = sigmap(wire); |