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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-09-14 12:43:18 +0200 |
|---|---|---|
| committer | N. Engelhardt <nak@symbioticeda.com> | 2020-09-14 12:43:18 +0200 |
| commit | 32381907972e16d5f72705eaf5350b731a9d71c8 (patch) | |
| tree | 73c08e35387cb9df6d69cf0d9129b03e115fd69c /passes/cmds | |
| parent | 4af04be0b7bb493a86a35a60f3b18d88df6b8ea9 (diff) | |
| download | yosys-32381907972e16d5f72705eaf5350b731a9d71c8.tar.gz yosys-32381907972e16d5f72705eaf5350b731a9d71c8.tar.bz2 yosys-32381907972e16d5f72705eaf5350b731a9d71c8.zip | |
use the new isPublic() in a few places
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/rename.cc | 4 | ||||
| -rw-r--r-- | passes/cmds/show.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/splice.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/stat.cc | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 6326b4b15..f8fe715c8 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -290,11 +290,11 @@ struct RenamePass : public Pass { dict<RTLIL::Cell *, IdString> new_cell_names; for (auto wire : module->selected_wires()) - if (wire->name[0] == '\\' && wire->port_id == 0) + if (wire->name.isPublic() && wire->port_id == 0) new_wire_names[wire] = NEW_ID; for (auto cell : module->selected_cells()) - if (cell->name[0] == '\\') + if (cell->name.isPublic()) new_cell_names[cell] = NEW_ID; for (auto &it : new_wire_names) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index a4ad861f6..0c96f8c5d 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -368,7 +368,7 @@ struct ShowWorker const char *shape = "diamond"; if (wire->port_input || wire->port_output) shape = "octagon"; - if (wire->name[0] == '\\') { + if (wire->name.isPublic()) { fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n", id2num(wire->name), shape, findLabel(wire->name.str()), nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str()); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 20627d601..0f63b91c5 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -211,7 +211,7 @@ struct SpliceWorker std::vector<Wire*> mod_wires = module->wires(); for (auto wire : mod_wires) - if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) { + if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) { if (!design->selected(module, wire)) continue; RTLIL::SigSpec sig = sigmap(wire); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index ed51fdc24..0d84c73db 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -81,7 +81,7 @@ struct statdata_t for (auto wire : mod->selected_wires()) { - if (wire->name[0] == '\\') { + if (wire->name.isPublic()) { num_pub_wires++; num_pub_wire_bits += wire->width; } |