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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 20:01:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 20:01:09 +0200 |
| commit | 3be5aac52c8703aa00ff591fd184da1ac39df678 (patch) | |
| tree | 1b9a402b5151ffb19b85287b4989489ce5c7a77d /libs | |
| parent | 9050b5e1915b05f55c1db279566f34202905f02a (diff) | |
| parent | 0e0c80fac883a6f512a94aecdc3c915b8cacb562 (diff) | |
| download | yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.tar.gz yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.tar.bz2 yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.zip | |
Merge pull request #953 from YosysHQ/clifford/fix948
Add support for zero-width signals to Verilog back-end
Diffstat (limited to 'libs')
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