diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 19:44:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-22 19:44:42 +0200 |
| commit | 0e0c80fac883a6f512a94aecdc3c915b8cacb562 (patch) | |
| tree | 1b9a402b5151ffb19b85287b4989489ce5c7a77d /libs | |
| parent | 9050b5e1915b05f55c1db279566f34202905f02a (diff) | |
| download | yosys-0e0c80fac883a6f512a94aecdc3c915b8cacb562.tar.gz yosys-0e0c80fac883a6f512a94aecdc3c915b8cacb562.tar.bz2 yosys-0e0c80fac883a6f512a94aecdc3c915b8cacb562.zip | |
Add support for zero-width signals to Verilog back-end, fixes #948
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'libs')
0 files changed, 0 insertions, 0 deletions