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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:49:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 (patch) | |
| tree | 8f736e6a2e208ed22d74c9f40cf9503dcd11c54c /kernel/rtlil.cc | |
| parent | 0bf9d0087c43f9db3d56cb2bed17268def21eb67 (diff) | |
| download | yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.tar.gz yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.tar.bz2 yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.zip | |
Add $specify2/$specify3 support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.cc')
0 files changed, 0 insertions, 0 deletions