From 96ad6888496f4cd34bbf461ce26f97f598bf898c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Dec 2017 21:48:31 +0100 Subject: Add SigSpec::is_fully_ones() --- kernel/rtlil.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8c3d2962c..7dc7107c1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,6 +3353,21 @@ bool RTLIL::SigSpec::is_fully_zero() const return true; } +bool RTLIL::SigSpec::is_fully_ones() const +{ + cover("kernel.rtlil.sigspec.is_fully_ones"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { + if (it->width > 0 && it->wire != NULL) + return false; + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::S1) + return false; + } + return true; +} + bool RTLIL::SigSpec::is_fully_def() const { cover("kernel.rtlil.sigspec.is_fully_def"); -- cgit v1.2.3