From 5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Apr 2020 09:44:24 -0700 Subject: Preserve 'signed'-ness of a verilog wire through RTLIL As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 196e301b6..98d6ed41f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1862,6 +1862,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth wire->port_input = other->port_input; wire->port_output = other->port_output; wire->upto = other->upto; + wire->is_signed = other->is_signed; wire->attributes = other->attributes; return wire; } @@ -2445,6 +2446,7 @@ RTLIL::Wire::Wire() port_input = false; port_output = false; upto = false; + is_signed = false; #ifdef WITH_PYTHON RTLIL::Wire::get_all_wires()->insert(std::pair(hashidx_, this)); -- cgit v1.2.3