From 081111714eed9cbc3dacac766cad85de30e98073 Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Mon, 20 Apr 2020 15:58:30 +0100 Subject: Simplify some RTLIL destructors No change in behaviour, but use range-based for loops instead of iterators. --- kernel/rtlil.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a756218f3..b7bef723f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -571,8 +571,8 @@ RTLIL::Design::Design() RTLIL::Design::~Design() { - for (auto it = modules_.begin(); it != modules_.end(); ++it) - delete it->second; + for (auto &pr : modules_) + delete pr.second; for (auto n : verilog_packages) delete n; for (auto n : verilog_globals) @@ -864,14 +864,14 @@ RTLIL::Module::Module() RTLIL::Module::~Module() { - for (auto it = wires_.begin(); it != wires_.end(); ++it) - delete it->second; - for (auto it = memories.begin(); it != memories.end(); ++it) - delete it->second; - for (auto it = cells_.begin(); it != cells_.end(); ++it) - delete it->second; - for (auto it = processes.begin(); it != processes.end(); ++it) - delete it->second; + for (auto &pr : wires_) + delete pr.second; + for (auto &pr : memories) + delete pr.second; + for (auto &pr : cells_) + delete pr.second; + for (auto &pr : processes) + delete pr.second; #ifdef WITH_PYTHON RTLIL::Module::get_all_modules()->erase(hashidx_); #endif -- cgit v1.2.3