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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-15 12:15:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 6f4f795953b2a38ec77984c7e1b50f579b59272e (patch) | |
| tree | 1f02c67304e08240b384a499954b7ed04daa5c81 /frontends/aiger | |
| parent | fb447951be5ac481106f06a911234614b576b40f (diff) | |
| download | yosys-6f4f795953b2a38ec77984c7e1b50f579b59272e.tar.gz yosys-6f4f795953b2a38ec77984c7e1b50f579b59272e.tar.bz2 yosys-6f4f795953b2a38ec77984c7e1b50f579b59272e.zip | |
aiger/xaiger: use odd for negedge clk, even for posedge
Since abc9 doesn't like negative mergeability values
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index ed3a926c6..16e94c394 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -789,13 +789,12 @@ void AigerReader::post_process() Cell* ff; int clock_index = mergeability[i]; - if (clock_index < 0) { + if (clock_index & 1) { ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index = -clock_index; + clock_index--; } - else if (clock_index > 0) + else ff = module->addCell(NEW_ID, ID($_DFF_P_)); - else log_abort(); auto r = mergeability_to_clock.insert(clock_index); if (r.second) r.first->second = module->addWire(NEW_ID); |