diff options
| -rw-r--r-- | backends/aiger/xaiger.cc | 16 | ||||
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 |
2 files changed, 13 insertions, 10 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index b8d65de4e..e2d8e1e7f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -627,21 +627,25 @@ struct XAigerWriter write_s_buffer(ff_bits.size()); dict<SigBit, int> clk_to_mergeability; + for (const auto &i : ff_bits) { + const Cell *cell = i.second; + log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_))); + + SigBit clock = sigmap(cell->getPort(ID::C)); + clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1)); + } for (const auto &i : ff_bits) { const SigBit &d = i.first; const Cell *cell = i.second; - log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_))); - SigBit clock = sigmap(cell->getPort(ID::C)); - auto r = clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size() + 1)); - int mergeability = r.first->second; + int mergeability = clk_to_mergeability.at(clock); log_assert(mergeability > 0); if (cell->type == ID($_DFF_N_)) - write_r_buffer(-mergeability); - else if (cell->type == ID($_DFF_P_)) write_r_buffer(mergeability); + else if (cell->type == ID($_DFF_P_)) + write_r_buffer(mergeability+1); else log_abort(); SigBit Q = sigmap(cell->getPort(ID::Q)); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index ed3a926c6..16e94c394 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -789,13 +789,12 @@ void AigerReader::post_process() Cell* ff; int clock_index = mergeability[i]; - if (clock_index < 0) { + if (clock_index & 1) { ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index = -clock_index; + clock_index--; } - else if (clock_index > 0) + else ff = module->addCell(NEW_ID, ID($_DFF_P_)); - else log_abort(); auto r = mergeability_to_clock.insert(clock_index); if (r.second) r.first->second = module->addWire(NEW_ID); |