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| author | Benjamin Barzen <bbarzen@barzen.io> | 2023-04-23 01:24:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-22 16:24:36 -0700 |
| commit | 861142923719aa84afc3bdf3c24a9a36e5d5fbaf (patch) | |
| tree | 6962a1e6128f3df3c099924942cb43ec2780b443 /backends/verilog | |
| parent | 7efc50367ed8f582001a5a293a9cd51f788f6a13 (diff) | |
| download | yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.tar.gz yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.tar.bz2 yosys-861142923719aa84afc3bdf3c24a9a36e5d5fbaf.zip | |
ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch
* Add simplified testcase
* Also fix xaiger writer for under-width output ports
* Remove old testcase
* Missing top-level input port
* Fix tabs
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions