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authorDavid Shah <davey1576@gmail.com>2018-12-07 17:17:26 +0000
committerGitHub <noreply@github.com>2018-12-07 17:17:26 +0000
commit435776120a40ed06ea42ca63bcca231913507ac3 (patch)
tree1509de1bf1e0413a23f48aaf066a69ea9068cb8f /backends/verilog
parent7d1088afc453f57f0ecc0f55ac2c91fd72ad8f2e (diff)
parent7ec740b7ad4ee4bc02e2564671e0153cdd08152f (diff)
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Merge pull request #727 from whitequark/opt_lut
opt_lut: leave intact LUTs with cascade feeding module outputs
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