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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 17:13:52 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2018-12-07 17:13:52 +0000 |
| commit | 7ec740b7ad4ee4bc02e2564671e0153cdd08152f (patch) | |
| tree | 1509de1bf1e0413a23f48aaf066a69ea9068cb8f /backends/verilog | |
| parent | 9eb03d458dcb2a3ba91a84739e764558b26e335c (diff) | |
| download | yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.tar.gz yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.tar.bz2 yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.zip | |
opt_lut: leave intact LUTs with cascade feeding module outputs.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions