From 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:14:02 +0200 Subject: More RTLIL::Cell API usage cleanups --- backends/spice/spice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 653a9f22d..077368771 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); if (cell->has(wire->name)) { - sig = sigmap(cell->connections().at(wire->name)); + sig = sigmap(cell->get(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); -- cgit v1.2.3