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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-25 09:04:43 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-25 09:04:43 +0200 |
| commit | b8624ad2aef941776f5b4a08f66f8d43e70f8467 (patch) | |
| tree | 83be1da1ecf7542916f6ced316ef62555ec0c2cf /Makefile | |
| parent | 52ba31b1c023b571868a396adfe1f43a0f71e867 (diff) | |
| download | yosys-b8624ad2aef941776f5b4a08f66f8d43e70f8467.tar.gz yosys-b8624ad2aef941776f5b4a08f66f8d43e70f8467.tar.bz2 yosys-b8624ad2aef941776f5b4a08f66f8d43e70f8467.zip | |
Compile option for enabling async load verific support
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -20,6 +20,7 @@ ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 DISABLE_VERIFIC_EXTENSIONS := 0 DISABLE_VERIFIC_VHDL := 0 +ENABLE_VERIFIC_ASYNC_LOAD := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 @@ -501,6 +502,9 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog database util containers hier_tree +ifeq ($(ENABLE_VERIFIC_ASYNC_LOAD),1) +CXXFLAGS += -DVERIFIC_ASYNC_LOAD +endif ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT |