From eb7b18e897ac908e960bee6c976f744043590881 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 11 Feb 2017 11:09:07 +0100
Subject: Fix extremely stupid typo

---
 frontends/verific/verific.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3f5cf3f5f..306bc5d82 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -774,7 +774,7 @@ struct VerificImporter
 
 				SigBit outsig = net_map.at(out);
 				log_assert(outsig.wire && GetSize(outsig.wire) == 1);
-				outsig.wire->attributes["\\init"] == Const(0, 1);
+				outsig.wire->attributes["\\init"] = Const(0, 1);
 
 				module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
 				continue;
-- 
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