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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-12 16:01:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-12 16:01:20 +0200 |
| commit | e7c018e5d14c3c609669ab514a7e9111ff006022 (patch) | |
| tree | 00bf6f097ff44b29eb795a6d05d6fe4d0eccb541 | |
| parent | 99ccb3180db7c391e902486d608040add5f3c31b (diff) | |
| download | yosys-e7c018e5d14c3c609669ab514a7e9111ff006022.tar.gz yosys-e7c018e5d14c3c609669ab514a7e9111ff006022.tar.bz2 yosys-e7c018e5d14c3c609669ab514a7e9111ff006022.zip | |
Fixed sharing of $memrd cells
| -rw-r--r-- | passes/opt/share.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 2c39708bb..9dd0dc0a3 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -708,6 +708,10 @@ struct ShareWorker if (c1->type == "$memrd") { RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); + RTLIL::SigSpec addr1 = c1->getPort("\\ADDR"); + RTLIL::SigSpec addr2 = c2->getPort("\\ADDR"); + if (addr1 != addr2) + supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act)); supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA"))); supercell_aux.insert(supercell); return supercell; |