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author | Clifford Wolf <clifford@clifford.at> | 2015-09-10 17:35:19 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-09-10 17:35:19 +0200 |
commit | 99ccb3180db7c391e902486d608040add5f3c31b (patch) | |
tree | 13d03342a73f05f8174dcdd46dfe4fa9aed748ba | |
parent | 6f9a6fd783dcca871ab89890aa9cde7add648f1e (diff) | |
download | yosys-99ccb3180db7c391e902486d608040add5f3c31b.tar.gz yosys-99ccb3180db7c391e902486d608040add5f3c31b.tar.bz2 yosys-99ccb3180db7c391e902486d608040add5f3c31b.zip |
Fixed ice40 handling of negclk RAM40
-rw-r--r-- | techlibs/ice40/brams_map.v | 8 | ||||
-rw-r--r-- | techlibs/ice40/cells_sim.v | 16 |
2 files changed, 12 insertions, 12 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index 8c5c7e812..f3674b4ed 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -90,7 +90,7 @@ module \$__ICE40_RAM4K ( .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (WCLK ), + .WCLKN(WCLK ), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), @@ -119,7 +119,7 @@ module \$__ICE40_RAM4K ( .INIT_F(INIT_F) ) _TECHMAP_REPLACE_ ( .RDATA(RDATA), - .RCLK (RCLK ), + .RCLKN(RCLK ), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), @@ -152,11 +152,11 @@ module \$__ICE40_RAM4K ( .INIT_F(INIT_F) ) _TECHMAP_REPLACE_ ( .RDATA(RDATA), - .RCLK (RCLK ), + .RCLKN(RCLK ), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (WCLK ), + .WCLKN(WCLK ), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 17b6be9ce..998ad3a1d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -473,7 +473,7 @@ endmodule module SB_RAM40_4KNR ( output [15:0] RDATA, - input RCLK, RCLKE, RE, + input RCLKN, RCLKE, RE, input [10:0] RADDR, input WCLK, WCLKE, WE, input [10:0] WADDR, @@ -520,7 +520,7 @@ module SB_RAM40_4KNR ( .INIT_F (INIT_F ) ) RAM ( .RDATA(RDATA), - .RCLK (~RCLK), + .RCLK (~RCLKN), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), @@ -537,7 +537,7 @@ module SB_RAM40_4KNW ( output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, - input WCLK, WCLKE, WE, + input WCLKN, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); @@ -586,7 +586,7 @@ module SB_RAM40_4KNW ( .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (~WCLK), + .WCLK (~WCLKN), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), @@ -597,9 +597,9 @@ endmodule module SB_RAM40_4KNRNW ( output [15:0] RDATA, - input RCLK, RCLKE, RE, + input RCLKN, RCLKE, RE, input [10:0] RADDR, - input WCLK, WCLKE, WE, + input WCLKN, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); @@ -644,11 +644,11 @@ module SB_RAM40_4KNRNW ( .INIT_F (INIT_F ) ) RAM ( .RDATA(RDATA), - .RCLK (~RCLK), + .RCLK (~RCLKN), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), - .WCLK (~WCLK), + .WCLK (~WCLKN), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), |