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authorEddie Hung <eddie@fpgeh.com>2019-06-21 17:21:06 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-21 17:21:06 -0700
commite67e78e9ac97a17d96e94c9627c1a58228e6d756 (patch)
treee4950276fc9982000d23fa1d04094c170da68cb0
parent588196c473f79cf2e221e86f1177d363a1849dcc (diff)
parentad296d77ab10266cd4b4df0779fbe7e5e0811c14 (diff)
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Merge remote-tracking branch 'origin/xaig' into xc7mux
-rw-r--r--CHANGELOG2
1 files changed, 1 insertions, 1 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 24c81be6e..51ff4e1a4 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,9 +22,9 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
+ - Added "synth -abc9" (experimental)
- Extended "muxcover -mux{4,8,16}=<cost>"
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
- - Added "synth -abc9" (experimental)
- Added "muxpack" pass
- "synth_xilinx" to now infer wide multiplexers (-nomux to disable)