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Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -22,9 +22,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) - Extended "muxcover -mux{4,8,16}=<cost>" - Fixed sign extension of unsized constants with 'bx and 'bz MSB - - Added "synth -abc9" (experimental) - Added "muxpack" pass - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) |