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| author | whitequark <whitequark@whitequark.org> | 2020-06-26 07:29:24 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-26 07:29:24 +0000 |
| commit | d6bdc09422e89c30207810cf00021b9ea37991e7 (patch) | |
| tree | 76e4da06f9e40b5626b1a2b35150cc2a1a68578b | |
| parent | c7d71f436d822bbbe3cda118591ed2b33eae3a7f (diff) | |
| parent | a8750b496e0bf7943abab813531cc3fba9b60352 (diff) | |
| download | yosys-d6bdc09422e89c30207810cf00021b9ea37991e7.tar.gz yosys-d6bdc09422e89c30207810cf00021b9ea37991e7.tar.bz2 yosys-d6bdc09422e89c30207810cf00021b9ea37991e7.zip | |
Merge pull request #2189 from antmicro/optional-labels
Add support for optional labels
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15c231f3b..4f3df575b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -435,7 +435,7 @@ module: mod->str = *$4; append_attr(mod, $1); delete $4; - } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE { + } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label { if (port_stubs.size() != 0) frontend_verilog_yyerror("Missing details for module port `%s'.", port_stubs.begin()->first.c_str()); @@ -556,7 +556,7 @@ package: current_ast_mod = mod; mod->str = *$4; append_attr(mod, $1); - } ';' package_body TOK_ENDPACKAGE { + } ';' package_body TOK_ENDPACKAGE opt_label { ast_stack.pop_back(); current_ast_mod = NULL; exitTypeScope(); |