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-rw-r--r--passes/techmap/hilomap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index a3261dccd..784c4cf31 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
- cell->set(RTLIL::escape_id(hicell_portname), last_hi);
+ cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
- cell->set(RTLIL::escape_id(locell_portname), last_lo);
+ cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;
}