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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-05-27 14:45:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-27 14:45:35 +0200 |
| commit | bf78041e8977effbce3a0928bfa22632222e8bbd (patch) | |
| tree | b67e102196e29aac04f8b208d82a14dc9cd58f58 | |
| parent | f9b6fe521dd9b7064ad7e576ffe779329f447e4f (diff) | |
| parent | 4316cdb60394efb04604d92f8f6f8e426cbc73f6 (diff) | |
| download | yosys-bf78041e8977effbce3a0928bfa22632222e8bbd.tar.gz yosys-bf78041e8977effbce3a0928bfa22632222e8bbd.tar.bz2 yosys-bf78041e8977effbce3a0928bfa22632222e8bbd.zip | |
Merge pull request #3341 from mmicko/unused_vars
Remove set but unused variable
| -rw-r--r-- | kernel/consteval.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index 642eb42b2..4c0c26049 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -146,7 +146,6 @@ struct ConstEval if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { std::vector<RTLIL::SigSpec> y_candidates; - int count_maybe_set_s_bits = 0; int count_set_s_bits = 0; if (!eval(sig_s, undef, cell)) @@ -160,9 +159,6 @@ struct ConstEval if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) y_candidates.push_back(b_slice); - if (s_bit == RTLIL::State::S1 || s_bit == RTLIL::State::Sx) - count_maybe_set_s_bits++; - if (s_bit == RTLIL::State::S1) count_set_s_bits++; } |