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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-27 12:37:03 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-27 12:37:03 +0200 |
| commit | 4316cdb60394efb04604d92f8f6f8e426cbc73f6 (patch) | |
| tree | 8d3c80e13808256e80af73ac681b3ee30f78bbfa | |
| parent | 5490f94e82180972e6534aed12c26e6575e35ec5 (diff) | |
| download | yosys-4316cdb60394efb04604d92f8f6f8e426cbc73f6.tar.gz yosys-4316cdb60394efb04604d92f8f6f8e426cbc73f6.tar.bz2 yosys-4316cdb60394efb04604d92f8f6f8e426cbc73f6.zip | |
Remove set but unused variable
| -rw-r--r-- | kernel/consteval.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index 642eb42b2..4c0c26049 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -146,7 +146,6 @@ struct ConstEval if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { std::vector<RTLIL::SigSpec> y_candidates; - int count_maybe_set_s_bits = 0; int count_set_s_bits = 0; if (!eval(sig_s, undef, cell)) @@ -160,9 +159,6 @@ struct ConstEval if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) y_candidates.push_back(b_slice); - if (s_bit == RTLIL::State::S1 || s_bit == RTLIL::State::Sx) - count_maybe_set_s_bits++; - if (s_bit == RTLIL::State::S1) count_set_s_bits++; } |