diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:23:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:31:09 -0700 |
| commit | b75863ca3f835595d75a6943de3cdd01fc91e4ca (patch) | |
| tree | b3e25f416c029f6e6c0c8f43d83a799cadbb4fa6 | |
| parent | bd7ec673dd5b542031698074e1043dcc32af2168 (diff) | |
| download | yosys-b75863ca3f835595d75a6943de3cdd01fc91e4ca.tar.gz yosys-b75863ca3f835595d75a6943de3cdd01fc91e4ca.tar.bz2 yosys-b75863ca3f835595d75a6943de3cdd01fc91e4ca.zip | |
Workaround issues exposed by gcc-4.8
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index a98ea8314..221e3edfc 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -117,13 +117,20 @@ struct ConstEvalAig RTLIL::Cell *cell = sig2driver.at(output); RTLIL::SigBit sig_a = cell->getPort("\\A"); + sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end()); if (!inputs.count(sig_a)) compute_deps(sig_a, inputs); if (cell->type == "$_AND_") { RTLIL::SigSpec sig_b = cell->getPort("\\B"); + sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end()); + if (!inputs.count(sig_b)) compute_deps(sig_b, inputs); } |