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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 12:46:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:31:09 -0700 |
| commit | bd7ec673dd5b542031698074e1043dcc32af2168 (patch) | |
| tree | 4a18be4a160a6c6fdf76d754c1a66249bff417db | |
| parent | 70c93ea0c4ce023d61553df11198aa0b7e518455 (diff) | |
| download | yosys-bd7ec673dd5b542031698074e1043dcc32af2168.tar.gz yosys-bd7ec673dd5b542031698074e1043dcc32af2168.tar.bz2 yosys-bd7ec673dd5b542031698074e1043dcc32af2168.zip | |
No point logging constant bit
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index aa10aa55e..6718e4f2c 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -110,7 +110,7 @@ struct XAigerWriter } if (bit == State::Sx || bit == State::Sz) { - log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); + log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n"); a = aig_map.at(State::S0); } |