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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-09-21 17:28:42 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-21 17:28:42 +0200 |
| commit | b2eb331b83072ec13377c8dc701e3dcf555255c1 (patch) | |
| tree | 308e82fe6d95bc37e6bb917c6722fcd96fed8042 | |
| parent | a217450524e21222d8d32bd448f1ea2291685258 (diff) | |
| parent | 8fb498744fbca326dba322d698dc75ee415f8edb (diff) | |
| download | yosys-b2eb331b83072ec13377c8dc701e3dcf555255c1.tar.gz yosys-b2eb331b83072ec13377c8dc701e3dcf555255c1.tar.bz2 yosys-b2eb331b83072ec13377c8dc701e3dcf555255c1.zip | |
Merge pull request #3487 from YosysHQ/micko/verific_mem_fix
Import memory attributes
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5eb4857c5..6e95fde7b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1176,6 +1176,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma memory->name = RTLIL::escape_id(net->Name()); log_assert(module->count_id(memory->name) == 0); module->memories[memory->name] = memory; + import_attributes(memory->attributes, net, nl); int number_of_bits = net->Size(); int bits_in_word = number_of_bits; |