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| author | clairexen <claire@symbioticeda.com> | 2020-06-25 16:40:30 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-25 16:40:30 +0200 |
| commit | 7d795d6fc7e81276c749300ded681c6d20a933b8 (patch) | |
| tree | 0313069f5ae57f3e717b5d7aab1577963e66dbfd | |
| parent | 0835a86e30fc2a934f5e6c96b28c90b59654ed92 (diff) | |
| parent | 4aec50a863b72b461352b84b15bdb9978c229db9 (diff) | |
| download | yosys-7d795d6fc7e81276c749300ded681c6d20a933b8.tar.gz yosys-7d795d6fc7e81276c749300ded681c6d20a933b8.tar.bz2 yosys-7d795d6fc7e81276c749300ded681c6d20a933b8.zip | |
Merge pull request #2192 from YosysHQ/verific_netbus_attr
verific - import attributes for net buses
| -rw-r--r-- | frontends/verific/verific.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1630c57bc..6637c214d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1109,7 +1109,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex()); - import_attributes(wire->attributes, netbus, nl); + MapIter mibus; + FOREACH_NET_OF_NETBUS(netbus, mibus, net) { + import_attributes(wire->attributes, net, nl); + break; + } RTLIL::Const initval = Const(State::Sx, GetSize(wire)); bool initval_valid = false; |