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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-25 09:18:53 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-25 09:18:53 +0200 |
| commit | 4aec50a863b72b461352b84b15bdb9978c229db9 (patch) | |
| tree | 0313069f5ae57f3e717b5d7aab1577963e66dbfd | |
| parent | f993d1875565c329689815a3bf63c6db76774c15 (diff) | |
| download | yosys-4aec50a863b72b461352b84b15bdb9978c229db9.tar.gz yosys-4aec50a863b72b461352b84b15bdb9978c229db9.tar.bz2 yosys-4aec50a863b72b461352b84b15bdb9978c229db9.zip | |
optimization, all items should have same attributes
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 89d734c40..6637c214d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1112,6 +1112,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se MapIter mibus; FOREACH_NET_OF_NETBUS(netbus, mibus, net) { import_attributes(wire->attributes, net, nl); + break; } RTLIL::Const initval = Const(State::Sx, GetSize(wire)); |