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| author | Clifford Wolf <clifford@clifford.at> | 2014-04-02 21:28:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-04-02 21:28:33 +0200 |
| commit | 7370ae01e978f0552f1565b88c0f44b402d09f4e (patch) | |
| tree | 954bbd3a5cee8578a96549fc0f7c5f13a0d60231 | |
| parent | e24797add0ceb0e8c3571cec9351a2b0120e9b19 (diff) | |
| download | yosys-7370ae01e978f0552f1565b88c0f44b402d09f4e.tar.gz yosys-7370ae01e978f0552f1565b88c0f44b402d09f4e.tar.bz2 yosys-7370ae01e978f0552f1565b88c0f44b402d09f4e.zip | |
Added SIMLIB_NOLUT to simlib.v
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 16e6a1b21..be9d24f18 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -927,6 +927,7 @@ end endmodule // -------------------------------------------------------- +`ifndef SIMLIB_NOLUT module \$lut (I, O); @@ -961,6 +962,7 @@ endgenerate endmodule +`endif // -------------------------------------------------------- module \$assert (A, EN); |