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| author | Clifford Wolf <clifford@clifford.at> | 2014-04-02 21:06:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-04-02 21:06:55 +0200 |
| commit | e24797add0ceb0e8c3571cec9351a2b0120e9b19 (patch) | |
| tree | cd8981e2d9f4aec3d675e55304ad0a4fb241aee1 | |
| parent | d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0 (diff) | |
| download | yosys-e24797add0ceb0e8c3571cec9351a2b0120e9b19.tar.gz yosys-e24797add0ceb0e8c3571cec9351a2b0120e9b19.tar.bz2 yosys-e24797add0ceb0e8c3571cec9351a2b0120e9b19.zip | |
Added SIMLIB_NOSR to simlib.v
| -rw-r--r-- | techlibs/common/simlib.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 908314f84..16e6a1b21 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -977,6 +977,7 @@ end endmodule // -------------------------------------------------------- +`ifndef SIMLIB_NOSR module \$sr (SET, CLR, Q); @@ -1003,6 +1004,7 @@ endgenerate endmodule +`endif // -------------------------------------------------------- module \$dff (CLK, D, Q); @@ -1022,6 +1024,7 @@ end endmodule // -------------------------------------------------------- +`ifndef SIMLIB_NOSR module \$dffsr (CLK, SET, CLR, D, Q); @@ -1053,6 +1056,7 @@ endgenerate endmodule +`endif // -------------------------------------------------------- module \$adff (CLK, ARST, D, Q); @@ -1096,6 +1100,7 @@ end endmodule // -------------------------------------------------------- +`ifndef SIMLIB_NOSR module \$dlatchsr (EN, SET, CLR, D, Q); @@ -1127,6 +1132,7 @@ endgenerate endmodule +`endif // -------------------------------------------------------- module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT); |