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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:07:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:07:33 -0700 |
| commit | 6b23c7c2277e6a79dd547f42854bfe4fbe8d5565 (patch) | |
| tree | e38a17f597a5cf8893fca50ab8d4c9cfe9fa0a4e | |
| parent | feb3fa65a3267acda76b7b6eea0e9ffedb281b85 (diff) | |
| parent | 97e1520b13231c8170cec73774eee7a22c5dc065 (diff) | |
| download | yosys-6b23c7c2277e6a79dd547f42854bfe4fbe8d5565.tar.gz yosys-6b23c7c2277e6a79dd547f42854bfe4fbe8d5565.tar.bz2 yosys-6b23c7c2277e6a79dd547f42854bfe4fbe8d5565.zip | |
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
| -rw-r--r-- | passes/pmgen/peepopt_shiftmul.pmg | 5 | ||||
| -rw-r--r-- | tests/various/peepopt.ys | 12 |
2 files changed, 9 insertions, 8 deletions
diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index d4748ae19..e1da52182 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -50,8 +50,9 @@ code if (GetSize(const_factor_cnst) > 20) reject; - if (GetSize(port(shift, \Y)) > const_factor) - reject; + if (shift->type.in($shift, $shiftx)) + if (GetSize(port(shift, \Y)) > const_factor) + reject; int factor_bits = ceil_log2(const_factor); SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 91db22423..33555264d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -5,7 +5,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shiftx @@ -16,16 +16,16 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <<EOT module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); -assign y = 1'b1 >> (w * (3'b110)); +assign y = 1'b1 >> (w * (8'b110)); endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 1 t:$mul +select -assert-count 0 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### @@ -40,7 +40,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 0 t:* @@ -55,7 +55,7 @@ endmodule EOT prep -nokeepdc -equiv_opt peepopt +equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$dff r:WIDTH=2 %i |