Merge remote-tracking branch 'origin/master' into xc7dsp

11 files changed, 397 insertions, 63 deletions

diff --git a/CHANGELOG b/CHANGELOG
index f0a0d0fae..50c611b8d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -38,6 +38,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improvements in pmgen: slices, choices, define, generate
     - Added "xilinx_srl" for Xilinx shift register extraction
     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+    - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
     - Added "xilinx_dsp" for Xilinx DSP packing
     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
diff --git a/Makefile b/Makefile
index 5e5c4e66e..492ef6ce2 100644
--- a/Makefile
+++ b/Makefile
@@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.9+231
+YOSYS_VER := 0.9+406
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 
diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 0856c9ba3..2f5b8d0b2 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -352,7 +352,7 @@ state variables used to pass arguments.
     subpattern tail
     ...
 
-Subpatterns cann be called recursively.
+Subpatterns can be called recursively.
 
 If a `subpattern` statement is preceded by a `fallthrough` statement, this is
 equivalent to calling the subpattern at the end of the preceding block.
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 5ce1bf7d6..51a65aea6 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -424,6 +424,18 @@ struct TechmapWorker
 
 		SigMap sigmap(module);
 
+		dict<SigBit, State> init_bits;
+		pool<SigBit> remove_init_bits;
+
+		for (auto wire : module->wires()) {
+			if (wire->attributes.count("\\init")) {
+				Const value = wire->attributes.at("\\init");
+				for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
+					if (value[i] != State::Sx)
+						init_bits[sigmap(SigBit(wire, i))] = value[i];
+			}
+		}
+
 		TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 		std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
 		std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
@@ -661,6 +673,17 @@ struct TechmapWorker
 									bit = RTLIL::SigBit(RTLIL::State::Sx);
 							parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
 						}
+						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
+							auto sig = sigmap(conn.second);
+							RTLIL::Const value(State::Sx, sig.size());
+							for (int i = 0; i < sig.size(); i++) {
+								auto it = init_bits.find(sig[i]);
+								if (it != init_bits.end()) {
+									value[i] = it->second;
+								}
+							}
+							parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
+						}
 					}
 
 					int unique_bit_id_counter = 0;
@@ -861,12 +884,25 @@ struct TechmapWorker
 
 					TechmapWires twd = techmap_find_special_wires(tpl);
 					for (auto &it : twd) {
-						if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
+						if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
 							log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
 						if (techmap_do_cache[tpl])
 							for (auto &it2 : it.second)
 								if (!it2.value.is_fully_const())
 									log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
+						if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) {
+							for (auto &it2 : it.second) {
+								auto val = it2.value.as_const();
+								auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+								auto it = cell->connections().find(wirename);
+								if (it != cell->connections().end()) {
+									auto sig = sigmap(it->second);
+									for (int i = 0; i < sig.size(); i++)
+										if (val[i] == State::S1)
+											remove_init_bits.insert(sig[i]);
+								}
+							}
+						}
 						techmap_wire_names.erase(it.first);
 					}
 
@@ -935,6 +971,25 @@ struct TechmapWorker
 			handled_cells.insert(cell);
 		}
 
+		if (!remove_init_bits.empty()) {
+			for (auto wire : module->wires())
+				if (wire->attributes.count("\\init")) {
+					Const &value = wire->attributes.at("\\init");
+					bool do_cleanup = true;
+					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
+						SigBit bit = sigmap(SigBit(wire, i));
+						if (remove_init_bits.count(bit))
+							value[i] = State::Sx;
+						else if (value[i] != State::Sx)
+							do_cleanup = false;
+					}
+					if (do_cleanup) {
+						log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
+						wire->attributes.erase("\\init");
+					}
+				}
+		}
+
 		if (log_continue) {
 			log_header(design, "Continuing TECHMAP pass.\n");
 			log_continue = false;
@@ -1047,6 +1102,13 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
 		log("\n");
+		log("    _TECHMAP_REMOVEINIT_<port-name>_\n");
+		log("        When this wire is set to a constant value, the init attribute of the wire(s)\n");
+		log("        connected to this port will be consumed.  This wire must have the same\n");
+		log("        width as the given port, and for every bit that is set to 1 in the value,\n");
+		log("        the corresponding init attribute bit will be changed to 1'bx.  If all\n");
+		log("        bits of an init attribute are left as x, it will be removed.\n");
+		log("\n");
 		log("In addition to this special wires, techmap also supports special parameters in\n");
 		log("modules in the map file:\n");
 		log("\n");
@@ -1060,6 +1122,13 @@ struct TechmapPass : public Pass {
 		log("        former has a 1-bit for each constant input bit and the latter has the\n");
 		log("        value for this bit. The unused bits of the latter are set to undef (x).\n");
 		log("\n");
+		log("    _TECHMAP_WIREINIT_<port-name>_\n");
+		log("        When a parameter with this name exists, it will be set to the initial\n");
+		log("        value of the wire(s) connected to the given port, as specified by the init\n");
+		log("        attribute. If the attribute doesn't exist, x will be filled for the\n");
+		log("        missing bits.  To remove the init attribute bits used, use the\n");
+		log("        _TECHMAP_REMOVEINIT_*_ wires.\n");
+		log("\n");
 		log("    _TECHMAP_BITS_CONNMAP_\n");
 		log("    _TECHMAP_CONNMAP_<port-name>_\n");
 		log("        For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2cf0e8e33..5f5aa5518 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -35,7 +35,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
deleted file mode 100644
index 4571f6d5c..000000000
--- a/techlibs/xilinx/ff_map.v
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-// FF mapping
-
-`ifndef _NO_FFS
-
-module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-
-module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
-
-module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
-module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-
-module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-
-`endif
-
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 83be66daa..3d92c3e2c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -273,6 +273,14 @@ struct SynthXilinxPass : public ScriptPass
 
 	void script() YS_OVERRIDE
 	{
+		std::string ff_map_file;
+		if (help_mode)
+			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+		else if (family == "xc6s")
+			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+		else
+			ff_map_file = "+/xilinx/xc7_ff_map.v";
+
 		if (check_label("begin")) {
 			if (vpr)
 				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
@@ -435,11 +443,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_ffs")) {
-				if (abc9 || help_mode) {
-						run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
-						run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-										"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)");
-				}
+			if (abc9 || help_mode) {
+				run("techmap -map " + ff_map_file, "('-abc9' only)");
+			}
 		}
 
 		if (check_label("map_luts")) {
@@ -472,15 +478,12 @@ struct SynthXilinxPass : public ScriptPass
 				run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
 			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
 			if (help_mode)
-				techmap_args += " [-map +/xilinx/ff_map.v]";
+				techmap_args += " [-map " + ff_map_file + "]";
 			else if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
 			else
-				techmap_args += " -map +/xilinx/ff_map.v";
+				techmap_args += " -map " + ff_map_file;
 			run("techmap " + techmap_args);
-			if (!abc9 || help_mode)
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
 			run("clean");
 		}
 
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
new file mode 100644
index 000000000..520a67579
--- /dev/null
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -0,0 +1,126 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// FF mapping
+
+`ifndef _NO_FFS
+
+module  \$_DFF_N_   (input D, C, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
+  else
+    FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+  endgenerate
+endmodule
+module  \$_DFF_P_   (input D, C, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
+  else
+    FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+  endgenerate
+endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .S(1'b0));
+  else
+    FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+  endgenerate
+endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .S(1'b0));
+  else
+    FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+  endgenerate
+endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+  else
+    FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+  endgenerate
+endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+  else
+    FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+  endgenerate
+endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+  else
+    FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+  endgenerate
+endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+    $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+  else
+    FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+  endgenerate
+endmodule
+
+module  \$_DFF_NN1_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+    $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+  else
+    FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+  endgenerate
+endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+    $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+  else
+    FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+  endgenerate
+endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+    $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+  else
+    FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+  endgenerate
+endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q);
+  parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+  generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+    $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+  else
+    FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+  endgenerate
+endmodule
+
+`endif
+
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
new file mode 100644
index 000000000..f6197b78b
--- /dev/null
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -0,0 +1,78 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// FF mapping
+
+`ifndef _NO_FFS
+
+module  \$_DFF_N_   (input D, C, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+endmodule
+module  \$_DFF_P_   (input D, C, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+endmodule
+
+module  \$_DFF_NN1_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q);
+  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+  FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+endmodule
+
+`endif
+
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index ecc2c8da8..e0acead82 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -204,7 +204,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -218,7 +218,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
@@ -232,7 +232,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
 
@@ -246,7 +246,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
 
@@ -260,7 +260,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=3 %i
 
@@ -274,7 +274,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
 
@@ -288,6 +288,6 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -keepdc
+equiv_opt -assert opt_expr -keepdc
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=13 %i
diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
new file mode 100644
index 000000000..1396839fe
--- /dev/null
+++ b/tests/techmap/wireinit.ys
@@ -0,0 +1,98 @@
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+
+endmodule
+EOT
+design -stash map
+
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
+
+endmodule
+EOT
+design -stash map_noremove
+
+read_verilog <<EOT
+module ffbb (...);
+parameter [0:0] INIT = 1'bx;
+input D, C;
+output Q;
+endmodule
+
+module top(...);
+input clk;
+input d;
+output reg q0 = 0;
+output reg q1 = 1;
+output reg qx;
+
+always @(posedge clk) begin
+	q0 <= d;
+	q1 <= d;
+	qx <= d;
+end
+endmodule
+EOT
+
+design -save ref
+
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map
+clean
+# Make sure the parameter was used properly.
+select -assert-count 2 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are dropped from the wires iff mapping was performed.
+select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
+
+design -load ref
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map_noremove
+clean
+# Make sure the parameter was used properly.
+select -assert-count 2 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are not dropped from the wires.
+select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i