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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 11:02:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 11:02:14 -0700 |
| commit | 65fa8adf6c834cc3c73300a19d4fe96c31b8d361 (patch) | |
| tree | 6fbd90e52841de774962434439e8a48d729ce419 | |
| parent | 29d446d7584b772a2dbac92a3088f93223ff7f86 (diff) | |
| download | yosys-65fa8adf6c834cc3c73300a19d4fe96c31b8d361.tar.gz yosys-65fa8adf6c834cc3c73300a19d4fe96c31b8d361.tar.bz2 yosys-65fa8adf6c834cc3c73300a19d4fe96c31b8d361.zip | |
Format macc.v
| -rw-r--r-- | tests/ice40/macc.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 6c3676c83..757c36a66 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -13,13 +13,13 @@ reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; assign c = reg_tmp_c; always @(posedge clk) begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end + if(set) + begin + reg_tmp_c <= 0; + end + else + begin + reg_tmp_c <= a * b + c; + end end endmodule |