diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 10:39:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 10:39:00 -0700 |
| commit | 29d446d7584b772a2dbac92a3088f93223ff7f86 (patch) | |
| tree | d4196c214feb705749272b867d50ba118a64d7a5 | |
| parent | c663a3680b13422c568e3dc438e7b971b81a71c3 (diff) | |
| download | yosys-29d446d7584b772a2dbac92a3088f93223ff7f86.tar.gz yosys-29d446d7584b772a2dbac92a3088f93223ff7f86.tar.bz2 yosys-29d446d7584b772a2dbac92a3088f93223ff7f86.zip | |
Cleanup
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 08cb1f51b..31ab75f09 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -398,10 +398,8 @@ endmatch code argQ argD { - if (clock != SigBit()) { - if (port(ff, \CLK) != clock) - reject; - } + if (clock != SigBit() && port(ff, \CLK) != clock) + reject; SigSpec Q = port(ff, \Q); if (ffoffset + GetSize(argQ) > GetSize(Q)) @@ -580,10 +578,8 @@ endmatch code argQ if (ff) { - if (clock != SigBit()) { - if (port(ff, \CLK) != clock) - reject; - } + if (clock != SigBit() && port(ff, \CLK) != clock) + reject; SigSpec D = port(ff, \D); if (ffoffset + GetSize(argD) > GetSize(D)) |