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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:45:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:45:51 -0700 |
| commit | 62fb3d5d15cedf84f6b977bf107cce56d36913af (patch) | |
| tree | f59474bedfa8fcd4a5eaa1c9195640a81465a64c | |
| parent | 06dcf7d08d10ab5cad164287b7ff7c75a96548ac (diff) | |
| download | yosys-62fb3d5d15cedf84f6b977bf107cce56d36913af.tar.gz yosys-62fb3d5d15cedf84f6b977bf107cce56d36913af.tar.bz2 yosys-62fb3d5d15cedf84f6b977bf107cce56d36913af.zip | |
Move wide mux from yosys-0.8 to 0.9
| -rw-r--r-- | CHANGELOG | 10 |
1 files changed, 2 insertions, 8 deletions
@@ -6,18 +6,13 @@ Yosys 0.9 .. Yosys 0.9-dev -------------------------- * Various - - Added "script -select" - - -Yosys 0.9 .. Yosys 0.9-dev --------------------------- - - * Various - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "script -select" + - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable) Yosys 0.8 .. Yosys 0.8-dev @@ -44,7 +39,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "synth_xilinx -nowidelut" - Added "synth_ecp5 -nowidelut" - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB |