From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:57:26 -0700 Subject: Add -assert --- tests/xilinx/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index b602b74d7..3bb3a8eb0 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -- cgit v1.2.3